The invention relates to the field of microprocessor architectures. Microprocessor designers are continually striving to improve microprocessor performance, designing microprocessor architectures that provide, for example, increased computational abilities, increased operating speeds, reduced power consumption, and/or reduced cost. With many previous microprocessor architectures, it has become increasingly difficult to improve microprocessor performance by increasing their operating frequency. As a result, many newer microprocessor architectures have focused on parallel processing to improve performance.
One parallel processing technique employed in microprocessor architectures is multiple processing cores. This technique utilizes multiple independent processors, referred to as cores, operating in parallel to execute software applications. Two or more processing cores may be implemented within the same integrated circuit die, within multiple integrated circuit dies integrated within the same integrated circuit package, or a combination of these implementations. Typically, multiple processing cores share a common interface and may share memory and other peripheral resources.
Often, a shared resource, such as shared memory or a peripheral, can only be used by one processor core at a time. To control access to shared resources, the processor cores can utilize synchronization primitives such as semaphores, flags, locks, atomic swaps, fetch and increment, or other signaling mechanisms. For example, a memory location may be used as a semaphore to ensure exclusive access to an associated shared resource, such as a critical section or region; a shared portion of memory; or a peripheral resource. A first processor core can check the state of the semaphore to determine if another processor core currently has exclusive access to the resource. If the semaphore value indicates that the resource is available, the first processor core can attempt to write its own indicator value to the semaphore memory location. This will indicate to other processor cores that the first processor core has exclusive access to the resource. The first processor core's write attempt will fail if another processor core modifies the value of the semaphore location before the first processor core's write is complete.
Two or more processor cores may attempt to access a synchronization primitive associated with a critical section or shared resource at approximately the same time. In some situations, each processor core's request for access to the synchronization primitive will cause the other pending access requests for the same memory location to fail. As a result, none of the processor cores will be able to acquire access to the synchronization primitive and its associated critical section or shared resource. Processor cores may then repeat their access requests, causing further access failures. The resulting condition is referred to as a synchronization livelock. In synchronization livelock, the processor cores are stuck in a circular chain of attempting and failing to acquire access to a synchronization primitive associated with a critical section or shared resource. Unless corrective action is taken to end the livelock, all of the involved processor cores may become stuck in a perpetual loop.
It is therefore desirable for systems and methods to prevent or recover from livelock in processors with multiple processor cores. It is further desirable for the systems and methods to have minimal impact on processor performance and complexity. It is further desirable for the systems and methods to work with both single and multithreaded processor cores.